1. Field of the Invention
The present invention relates to a content addressable memory for operating at a high speed even though the number of data of retrieval is increased.
2. Description of the Prior Art
There are memory cells of Content Adressable Memory (referred to as CAM hereinafter) having an associative function, such as TLB (Translation Lookaside Buffer), BTB (Banch Target Buffer), and the like, as shown in FIGS. 1 and 2.
In the same diagrams, a CAM cell 5 is composed of a cell portion 1 selected by a word line 4 for storeing an information given from a data line 6, and an Exclusive OR (XOR) portion 3 for comparing the information in the cell 1 and a retrieval data given from a retrieval line 8.
In such the composition of the conventional CAM cell 5, it compares the retrieval data with a content of the information in the cell portion 1 at the XOR portion 3 for detecting whether they agree or not. The result of the retrieval operation is output through a matching line (a retrieval output line) 2.
The CAM is made up of the CAM cells 5 having the above mentioned composition arranging like a matrix, as shown in FIG. 3. A CAM cell array as shown in the same diagram are arranged the CAM cells 5 in seven lines and eight rows. In this case, a maximum retrieval data is eight bits. Namely, the eight memory cells (per one row) are connected to the same word line 4 and the same matching line 2. Accordingly, a retrieval data of the eight bits connected to the same word line 4 at the CAM cells 5 is output to the common matching line 2. When the CAM is operated dynamically, the matching line 2 is setted in a precharge state by a precharge transistor 7 controlled in synchronization with a clock signal (CLK) .phi.. On the other hand, when the CAM is operated statically, the matching line 2 is connected to a power source (a symbol ".gradient." as shown in FIG. 3) through a load transistor 9 which is always kept in electrical continuity.
In the above mentioned composition, a verification between the retrieval data and the information in the CAM cell 5 output to the word line 4 is performed at the same time on all word lines (see in FIG. 3). When the retrieval data and the information in the memory cells 5 per the row are same, the matching line 2 connected to the CAM cells 5 in the row becomes high-level (referred to as H-level hereinafter) and thereby a retrieval result as a success to retrieve is output to outside of the CAM.
While, the matching line 2 of the CAM cells 5, in which different information from the retrieval data in content is stored, connected to the same word line 4 becomes low-level (referred to as L-level hereinafter) so that a retrieval results as a failure to retrieve is output to outside of the CAM.
The CAM of the composition as shown in the FIG. 3, when the number of bits of the retrieval data is increased, the number of CAM cells connected to the same word line is increased. Similarly, the number of CAM cells connected to the same matching line is also increased. By the way, there is a drain capacity, as a load capacity, of a field effect transistor (FET) in the XOR portion 3 connected to the matching line 2. Accordingly, when the number of the CAM cells connected to the matching line 2 is increased, the number of the FET connected to the matching line 2 is increased and thereby the load capacity of the matching line 2 is increased.
For instance, when the number of the bits of the retrieval data is twice, the load capacity of the matching line becomes about twice. Accordingly, when a failure of a retrieval operation occures, it takes longer for changing from the H-level to the L-level on the matching line 2. Thereby a retrieval speed is decreased and to execute a retrieval operation at a high speed in the CAM therefore becomes more dificult.